Analog & Chiptop Design Engineer Apply for this position

Responsibilities

• You will work on productization of sensors: This will include chiptop level design of the sensor with considerations to physical requirements (chip size, block/pad locations), electrical requirement (power/clock distribution, ESD, noise), and optical requirements.
• You will perform full-cycle follow-up from conception to design to verifications.
• You implement the TOP level of the sensor (IO pads, ESD IO body, connectivity of stacked wafers) based on the daily interaction with design teams (analog, logic, pixel) and optimize based on the feedback from Implementation/Back-end, Package and Device teams.
• You are responsible for the ESD protection of the sensor and support the mask improvement after the tape out.
• You are the interface among the Design environment, the Device and the Design team.

Qualifications

• You have a strong command of English.
• You have a master’s degree in electrical engineering or similar by experience.
• You have more than 5 years’ experience in the analog/chiptop design domain with responsibilities as described above.
• You have a background in analog design engineering with proven experience on layout design at top level of chips with recent technology nodes.
• You will require an analytical mind with a strong commitment to quality and high team spirit and social skills as you will be working with design teams, and hardware and software engineers to successfully complete challenging IC and sensor system design projects.
• This position requires strong communications skills: Ability to communicate and work efficiently with various IC design teams (analog, logic, pixel, verification etc.) is very important.
• You are familiar with the design of complex analog blocks such as ADC, DAC, PLL, bias generator, gain amplifiers, and comparators. Knowledge of image sensor functions a plus.

• You are experienced in Cadence Virtuoso schematic. Know-how on layout is a mandatory.

• You are experienced in implementing protection circuits for ESD tests and requirements (HBM, CDM).

• You understand the concepts of power analysis, clock distribution, IR drop measurement.
• You have knowledge in wafer, package and assembly process (for example Hot carrier light blocking, Plasma-induced damage, band noise, mask improvement support…).

• You have experience with LVS / DRC at block and full chip level using tools like Assura and Calibre.
• You are familiar with full physical verification flow and tools.
• You are familiar with parasitic extraction using tools like Cadence QRC, Synopsys StarRC.

• Ability to write script in Unix, SKILL or Ocean is a plus.

• You have knowledge of simulation analysis of analog blocks including a deep understanding of basic (R/L/C/Tr) element fabrication process, simulation models and model accuracy.

• You are goal oriented and have an innovative approach to problem solving.
• You are willing to travel internationally if needed.
• Japanese language skills are a strong advantage.
• Planning skills are also needed for this position.
• Strong commitment is necessary, especially close to the release milestone.

Benefits

• International – With more than 30 nationalities under the same roof, you will evolve in a very open-minded and multi-cultural environment with English as lingua franca.
• Ideally situated – Located in the heart of the beautiful city of Brussels, our offices are easily accessible by public transport and surrounded by many restaurants and shops.
• Dynamic environment – You will be part of a very dynamic and young team where your ideas are heard and where you will be able to make a difference.
• Training – On top of a yearly budget allowing to take a training in any subject, regular internal presentations and workshops will keep you up-to-date with the latest technologies.