Job Description

Job Description

Sony Depthsensing Solutions is seeking a Top Design Engineer to work on next generation image sensor designs and architectures in their Brussels location.

This position is part of an advanced technology team which is enabling the next generation of image sensors. The successful candidate will bring their deep knowledge and proven experience in sensor design to yield the highest quality of first silicon success.

Your main focus will be on the top level design of SDS sensors.


  • You will work on R&D of image sensors: This will include top level design of the sensor with considerations to physical requirements (chip size, block/pad locations), electrical requirement (power/clock distribution, ESD, noise), and optical requirements.
  • You will perform full-cycle follow-up from conception to design to validation in silicon to volume production.
  • You implement the TOP level of the sensor (floorplan, block and I/O pads placement, ESD protection design) based on the daily interaction with design teams (analog, logic, pixel) and optimize based on the feedback from Back-end, Package and Device teams.
  • You are responsible for the ESD protection of the sensor and support the mask improvement after the tape out.
  • You are the interface among the Design environment (PDK support), the Device and the Design teams.


▪ You have a strong command of English.
▪ You have a master’s degree in electrical engineering or similar by experience.
▪ You will require an analytical mind with a strong commitment to quality and a high sense of team spirit and social skills as you will be working with design teams, hardware and software engineers to successfully complete challenging IC and sensor system design projects.
▪ This position requires strong communications skills: Ability to communicate and work efficiently with various IC design teams (analog, logic, pixel, verification etc.) is very important.
▪ You are familiar with the design of complex analog blocks such as ADC, DAC, PLL, bias generator, gain amplifiers, and comparators. Knowledge of image sensor functions a plus.
▪ You are experienced in Cadence Virtuoso schematic & layout flow and tools.
▪ You have experienced in implementing protection circuits for ESD tests and requirements (HBM, CDM).
▪ You understand the concepts of power analysis, clock distribution, IR drop measurement.
▪ You have knowledge in wafer, package and assembly process (for example Hot carriers, Plasma-induced damage, noise coupling, optical shielding, mask improvement support…).
▪ You have experience with LVS / DRC at block and full chip level using tools like Assura and Calibre.
▪ You are familiar with full physical verification flow and tools.
▪ You are familiar with parasitic extraction using tools like Cadence QRC, Synopsys StarRC.
▪ Able to write script in Unix is a plus.
▪ You have knowledge of simulation analysis of analog blocks including a deep understanding of basic (R/L/C/Tr) element fabrication process, simulation models and model accuracy.
▪ You are goal oriented and innovative approach to problem solving.
▪ You are willing to travel internationally if needed.
▪ Japanese language skills are a strong advantage.
▪ Strong commitment is necessary, especially close to the release milestone.


  • International – With more than 30 nationalities under the same roof, you will evolve in a very open-minded and multi-cultural environment with English as lingua franca.
  • Ideally situated – Located in the heart of the beautiful city of Brussels, our offices are easily accessible by public transport and surrounded by many restaurants and shops.
  • Dynamic environment – You will be part of a very dynamic and young team where your ideas are heard and where you will be able to make a difference.
  • Training – On top of a yearly budget allowing to take a training in any subject, regular internal presentations and workshops will keep you up-to-date with the latest technologies.
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Then this would happen (after reviewing resume)

A first call with the Hiring Manager

In-depth call or face to face interview with HR

Technical assignment

Follow-up interview with members of the team

Contract proposal

Contact us!

Yee Yan Cheung / Senior HR Officer
Boulevard de la Plaine 11 Pleinlaan
1050 Bruxelles/Brussels Belgium

Top Design Engineer

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