Chiptop/Layout Design Engineer Apply for this position

Responsibilities

• As a main duty, this will include support of top level design of the sensor with considerations to physical requirements (chip size, block/pad locations), electrical requirement (power/clock distribution, ESD, noise), and optical requirements.
• You will support full-cycle follow-up from conception to design to validation in silicon to volume production.
• You will support the implementation of the TOP level of the sensor based on the daily interaction with design teams (analog, logic, pixel). This involves block integration, padring and IO design, as well as floor planning work.
• You perform optimizations based on the feedback from Physical Implementation/Back-end, Package and Device teams.
• You will support the design of ESD protection of the sensor. You support the mask improvement after the tape out. You are part of  the team who is the interface among the Design environment, the Device and the Design teams.
• As a secondary duty, you can perform layout design of analog blocks.

Qualifications

• You have a strong command of English.
• You have a master’s degree in electrical engineering or similar by experience.
• You have strong communication skills and are team-oriented: Ability to interface and work efficiently with various IC design teams (analog, logic, pixel, verification, package, implementation etc.) is key to successfully completing challenging IC and sensor system design projects.
• You are proactive, solution-oriented and a constructive thinker.
• You are committed to delivering on time and with quality.

• You are experienced in Cadence Virtuoso schematic and layout.

• You are experienced in running LVS / DRC at block and full chip level, using tools like Assura and Calibre.
• You are familiar with layout techniques for yield and reliability.
• You understand analog-driven layout constraints (parasitics, impedances, decoupling, signal shielding, etc… ).
• You understand the ESD concepts and can drive the ESD strategy of a die.
• Experience in implementing protection circuits for ESD tests and requirements (HBM, CDM) is a plus.

• Coding skills (skill, bash, python, etc..) is a plus.
• You are familiar with parasitic extraction flows and tools (Cadence QRC, Synopsys StarRC).
• You understand the concepts of power analysis, clock distribution, IR drop measurement.
• You have knowledge in wafer, package and assembly process (for example Hot carrier light blocking, Plasma-induced damage, band noise, mask improvement support…).
• Knowledge of image sensor functions is a plus.

• Familiarity with analog blocks such as ADC, DAC, PLL, bias generator, gain amplifiers, and comparators is a strong plus.
• You have knowledge of simulation analysis of analog blocks including a deep understanding of basic (R/L/C/Tr) element fabrication process, simulation models and model accuracy.

• You are willing to travel internationally if needed.
• Japanese language skills are a strong advantage.
• Strong commitment is necessary, especially close to the release milestone.

Benefits

• International – With more than 30 nationalities under the same roof, you will evolve in a very open-minded and multi-cultural environment with English as lingua franca.
• Ideally situated – Located in the heart of the beautiful city of Brussels, our offices are easily accessible by public transport and surrounded by many restaurants and shops.
• Dynamic environment – You will be part of a very dynamic and young team where your ideas are heard and where you will be able to make a difference.
• Training – On top of a yearly budget allowing to take a training in any subject, regular internal presentations and workshops will keep you up-to-date with the latest technologies.