Job

ANALOG DESIGN ENGINEER

Job Description

Sony Depthsensing Solutions is seeking an Analog Design Engineer to work on next generation Time of Flight (TOF) sensor designs and architectures in their Brussels location.

This position is part of an advanced technology team which is enabling the next generation of Time of Flight imaging.  The successful candidate will bring their deep knowledge and proven experience in analog design of complex analog blocks and full chips to yield the highest quality of first silicon success. Your main focus will be on advanced analog and mixed-signal integrated circuits for TOF sensors.

 

Responsibilities:

  • You will work on R&D on TOF sensors, circuits, and pixels: This will include full-cycle follow-up from conception to design to validation in silicon to volume production.
  • You will work with other members of the design team on the analysis, design, verification and evaluation of TOF sensors.
  • You will do verification of sensor functionality and performance: You will work with characterization teams to help provide understanding of the characterization analysis and to tune simulation models.

 

QUALIFICATIONS

  • You have a strong command of English.
  • You have a masters degree in electrical engineering or similar by experience
  • You will require an analytical mind with a strong commitment to quality within high team spirit and social skills as you will be working with design teams, hardware and software engineers to successfully complete challenging IC and sensor system design projects.
  • You ideally have 3-5 years of experience with the design of complex analog blocks such as ADC, DAC, PLL, bias generator, gain amplifiers, and comparators. Knowledge of image sensor functions a plus.
  • You are an expert in design from scratch of analog blocks including architectural analysis, noise, power, and area analysis, schematic entry and critical simulation analysis
  • You have experience with the full design flow including Cadence layout from early schematics, area estimation, full layout, parasitic extraction, ECO implementation
  • You are skilled with SPICE simulator types with deep knowledge of tradeoffs such as power modeling, SPICE and fast SPICE, noise, transient, and monte carlo simulations
  • You have knowledge of simulation analysis of analog blocks including a deep understanding of basic (R/L/C/Tr) element fabrication process, simulation models and model accuracy
  • You have experience with LVS / DRC at block and full chip level using tools like Assura and Calibre
  • You are familiar with full physical verification flow and tools
  • You are familiar with parasitic extraction using tools like Cadence QRC, Synopsys StarRC
  • You have experience with power analysis, IR drop measurement, power planning, top level layout of full chips
  • You are goal oriented and innovative approach to problem solving.
  • You are willing to travel internationally if needed
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